| 000 | 00706nam a2200229 a 4500 | ||
|---|---|---|---|
| 001 | 000300953 | ||
| 005 | 20190826143947.0 | ||
| 008 | 141109s2014 deua f 000 0 eng d | ||
| 020 | _a9781500385781 | ||
| 050 | 4 |
_aTK7885.7 _bT462L |
|
| 100 | 1 | _aThomas, Donald | |
| 245 | 1 | 0 |
_aLogic design and verification using SystemVerilog / _cDonald Thomas. |
| 260 |
_aMiddletown, De. : _bCreateSpace, _c2014. |
||
| 300 |
_a303 p. : _bill. |
||
| 500 | _aIncludes index | ||
| 650 | 0 | _aVerilog (Computer hardware description language) | |
| 650 | 0 |
_aElectronic digital computers _xDesign and construction |
|
| 650 | 0 | _aComputer simulation | |
| 990 |
_aA54083 _b20150112 |
||
| 991 |
_a07 _b01 |
||
| 942 |
_2lcc _cBK |
||
| 999 |
_c244931 _d244931 |
||